A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element, and one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements, where the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements and the plurality of execution clusters.