Invention Grant
- Patent Title: Transistor fabrication method
- Patent Title (中): 晶体管制造方法
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Application No.: US12689749Application Date: 2010-01-19
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Publication No.: US08030199B2Publication Date: 2011-10-04
- Inventor: Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
- Applicant: Sailesh Chittipeddi , Taeho Kook , Avinoam Kornblit
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
Public/Granted literature
- US20100120216A1 TRANSISTOR FABRICATION METHOD Public/Granted day:2010-05-13
Information query
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