Invention Grant
- Patent Title: Bonding method for through-silicon-via based 3D wafer stacking
- Patent Title (中): 基于硅通孔的3D晶片堆叠的粘合方法
-
Application No.: US12131777Application Date: 2008-06-02
-
Publication No.: US08030208B2Publication Date: 2011-10-04
- Inventor: Chi Kuen Vincent Leung , Peng Sun , Xunqing Shi , Chang Hwa Chung
- Applicant: Chi Kuen Vincent Leung , Peng Sun , Xunqing Shi , Chang Hwa Chung
- Applicant Address: HK Shatin, New Territories
- Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
- Current Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
- Current Assignee Address: HK Shatin, New Territories
- Agency: Wells St. John, P.S.
- Main IPC: H01L21/4763
- IPC: H01L21/4763
Abstract:
There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.
Public/Granted literature
- US20090294974A1 BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING Public/Granted day:2009-12-03
Information query
IPC分类:
