A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.