Invention Grant
US08030709B2 Metal gate stack and semiconductor gate stack for CMOS devices
有权
CMOS器件的金属栅极堆叠和半导体栅极堆叠
- Patent Title: Metal gate stack and semiconductor gate stack for CMOS devices
- Patent Title (中): CMOS器件的金属栅极堆叠和半导体栅极堆叠
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Application No.: US11954918Application Date: 2007-12-12
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Publication No.: US08030709B2Publication Date: 2011-10-04
- Inventor: Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
- Applicant: Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
- Applicant Address: US NY Armonk KY Grand Cayman
- Assignee: International Business Machines Corporation,Globalfoundries, Inc.
- Current Assignee: International Business Machines Corporation,Globalfoundries, Inc.
- Current Assignee Address: US NY Armonk KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/148 ; H01L27/12 ; H01L21/84 ; H01L21/338

Abstract:
A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
Public/Granted literature
- US20090179283A1 METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES Public/Granted day:2009-07-16
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