Invention Grant
- Patent Title: Method of manufacturing semiconductor package and semiconductor plastic package using the same
- Patent Title (中): 使用其制造半导体封装和半导体塑料封装的方法
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Application No.: US12213796Application Date: 2008-06-24
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Publication No.: US08030752B2Publication Date: 2011-10-04
- Inventor: Nobuyuki Ikeguchi , Keungjin Sohn , JoonSik Shin , Jung-Hwan Park
- Applicant: Nobuyuki Ikeguchi , Keungjin Sohn , JoonSik Shin , Jung-Hwan Park
- Applicant Address: KR Suwon
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon
- Priority: KR10-2007-0133242 20071218; KR10-2007-0134335 20071220
- Main IPC: H01L23/04
- IPC: H01L23/04 ; H01L23/12

Abstract:
A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.
Public/Granted literature
- US20090152742A1 Method of manufacturing semiconductor package and semiconductor plastic package using the same Public/Granted day:2009-06-18
Information query
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