A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing a first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch.