Invention Grant
US08030971B2 High-density logic techniques with reduced-stack multi-gate field effect transistors
有权
具有减少堆叠多栅极场效应晶体管的高密度逻辑技术
- Patent Title: High-density logic techniques with reduced-stack multi-gate field effect transistors
- Patent Title (中): 具有减少堆叠多栅极场效应晶体管的高密度逻辑技术
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Application No.: US12102097Application Date: 2008-04-14
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Publication No.: US08030971B2Publication Date: 2011-10-04
- Inventor: Meng-Hsueh Chiang , Ching-Te Kent Chuang , Keunwoo Kim
- Applicant: Meng-Hsueh Chiang , Ching-Te Kent Chuang , Keunwoo Kim
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Main IPC: H03K19/20
- IPC: H03K19/20 ; H03K19/094
Abstract:
Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
Public/Granted literature
- US20100026346A1 HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS Public/Granted day:2010-02-04
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