A main (sub) clock circuit comprising a first (second) capacitor, a first (second) current-supply circuit to supply to the first (second) capacitor a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at a predetermined-current value, a first (second) charge/discharge-control circuit to output a first (second) control signal for switching between the first (third) current and second (fourth) current which are supplied to the first (second) capacitor from the first (second) current-supply circuit when a voltage across the first (second) capacitor has reached a first (third) reference voltage or second (fourth) reference voltage higher than the first (third) reference voltage, and a first (second) output circuit to output a main (sub) clock according to the first (second) control signal, the first capacitor having one end connected to a first potential, the second capacitor having one end to which the main clock is input.