Invention Grant
- Patent Title: Phase-locked loop circuit
- Patent Title (中): 锁相环电路
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Application No.: US10590644Application Date: 2005-02-14
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Publication No.: US08031015B2Publication Date: 2011-10-04
- Inventor: Syuji Kimura , Takashi Hashizume
- Applicant: Syuji Kimura , Takashi Hashizume
- Applicant Address: JP Osaka
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: SoCal IP Law Group LLP
- Agent Steven C. Sereboff; John E. Gunther
- Priority: JP2004-055280 20040227
- International Application: PCT/JP2005/002156 WO 20050214
- International Announcement: WO2005/083887 WO 20050909
- Main IPC: H03B29/00
- IPC: H03B29/00

Abstract:
A PLL circuit is disclosed that comprises a controlling unit that switches at a predetermined timing to enable/disable the phase difference signal supplied from the phase comparator to the low pass filter; and a resistor element that is disposed between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter, when the phase difference signal is enabled, the oscillation circuit performing oscillation operation based on the voltage signal corresponding to the phase difference signal, when the phase difference signal is disabled, the low pass filter being supplied with the predetermined potential through the resistor element to allow the oscillation circuit to perform oscillation operation based on the voltage signal generated depending on the supplied predetermined potential.
Public/Granted literature
- US20080278248A1 Pll Circuit Public/Granted day:2008-11-13
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