Invention Grant
US08031098B1 DAC circuit with pseudo-return-to-zero scheme and DAC calibration circuit and method
有权
DAC电路采用伪归零方案和DAC校准电路及方法
- Patent Title: DAC circuit with pseudo-return-to-zero scheme and DAC calibration circuit and method
- Patent Title (中): DAC电路采用伪归零方案和DAC校准电路及方法
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Application No.: US12689874Application Date: 2010-01-19
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Publication No.: US08031098B1Publication Date: 2011-10-04
- Inventor: Christian Ebner , Jipeng Li , Bernd Schafferer
- Applicant: Christian Ebner , Jipeng Li , Bernd Schafferer
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Law Group LLP
- Agent Carmen C. Cook
- Main IPC: H03M1/72
- IPC: H03M1/72

Abstract:
In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-ΣΔ) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.
Information query
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