The configuration of a synchronous rectification circuit and a controlling method thereof are provided. The proposed circuit includes a converter including a first switch and a first synchronous rectifier, and a burst mode controller including a logic process module performing one of functions of delaying one of a non-integer and at least one operating periods to generate a synchronous rectification driving signal of the first synchronous rectifier counting from a beginning of a first pulse of a driving signal of the first switch during a working time of a burst period, and turning off the synchronous rectification driving signal of the first synchronous rectifier by one of the non-integer operating period and the at least one operating period ahead of an ending of a last operating period of the driving signal of the first switch during the working time of the burst period.