Invention Grant
- Patent Title: Flash memory programming and verification with reduced leakage current
- Patent Title (中): 闪存编程和验证,减少漏电流
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Application No.: US12557721Application Date: 2009-09-11
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Publication No.: US08031528B2Publication Date: 2011-10-04
- Inventor: Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
- Applicant: Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/04

Abstract:
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
Public/Granted literature
- US20100027350A1 FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT Public/Granted day:2010-02-04
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