Invention Grant
- Patent Title: Low read current architecture for memory
- Patent Title (中): 低读取存储体系结构
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Application No.: US12799168Application Date: 2010-04-19
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Publication No.: US08031545B2Publication Date: 2011-10-04
- Inventor: Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
- Applicant: Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
- Assignee: Unity Semiconductor Corporation
- Current Assignee: Unity Semiconductor Corporation
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
Public/Granted literature
- US20100202188A1 Low read current architecture for memory Public/Granted day:2010-08-12
Information query
