Invention Grant
- Patent Title: Receiver device, error detection circuit, and receiving method
- Patent Title (中): 接收装置,误差检测电路和接收方式
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Application No.: US12117439Application Date: 2008-05-08
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Publication No.: US08031817B2Publication Date: 2011-10-04
- Inventor: Ryousuke Watanabe
- Applicant: Ryousuke Watanabe
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Arent Fox LLP
- Main IPC: H03D1/00
- IPC: H03D1/00

Abstract:
A receiver device which is small in scale of circuit configuration yet capable of detecting an error between symbol timing of a received signal and that generated therein and also restraining an error signal from varying due to variation in input level of the received signal. A delayer delays the received signal for one effective symbol period, a correlator calculates a correlation signal from the product of the received signal and the delayed signal, and an integrator calculates an integral value of the correlation signal. First and second accumulative adders accumulatively add up the integral values over respective predetermined periods before and after symbol start timing generated within the receiver device. An error signal generator generates an error signal by normalizing the difference between first and second sums obtained from the first and second accumulative adders, respectively, by means of the sum total of the first and second sums.
Public/Granted literature
- US20090185645A1 Receiver Device, Error Detection Circuit, and Receiving Method Public/Granted day:2009-07-23
Information query
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