In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.