Invention Grant
- Patent Title: Semiconductor integrated circuit and test system thereof
- Patent Title (中): 半导体集成电路及其测试系统
-
Application No.: US12164518Application Date: 2008-06-30
-
Publication No.: US08032803B2Publication Date: 2011-10-04
- Inventor: Kenichi Anzou , Chikako Tokunaga
- Applicant: Kenichi Anzou , Chikako Tokunaga
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2007-187937 20070719
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/00

Abstract:
A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the memory cell, output expected value data, and decide whether to continue a test or suspend the test to output failure information to outside, based on a comparison result of the data pattern outputted from the memory cell and the expected value data and a comparison result of the data pattern and the failed data pattern.
Public/Granted literature
- US20090024885A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST SYSTEM THEREOF Public/Granted day:2009-01-22
Information query