Invention Grant
US08032803B2 Semiconductor integrated circuit and test system thereof 有权
半导体集成电路及其测试系统

Semiconductor integrated circuit and test system thereof
Abstract:
A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the memory cell, output expected value data, and decide whether to continue a test or suspend the test to output failure information to outside, based on a comparison result of the data pattern outputted from the memory cell and the expected value data and a comparison result of the data pattern and the failed data pattern.
Public/Granted literature
Information query
Patent Agency Ranking
0/0