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US08032855B1 Method and apparatus for performing incremental placement on a structured application specific integrated circuit 有权
用于在结构化专用集成电路上执行增量放置的方法和装置

  • Patent Title: Method and apparatus for performing incremental placement on a structured application specific integrated circuit
  • Patent Title (中): 用于在结构化专用集成电路上执行增量放置的方法和装置
  • Application No.: US11295354
    Application Date: 2005-12-06
  • Publication No.: US08032855B1
    Publication Date: 2011-10-04
  • Inventor: Andrew C. Ling , Deshanand Singh
  • Applicant: Andrew C. Ling , Deshanand Singh
  • Applicant Address: US CA San Jose
  • Assignee: Altera Corporation
  • Current Assignee: Altera Corporation
  • Current Assignee Address: US CA San Jose
  • Agent L. Cho
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Method and apparatus for performing incremental placement on a structured application specific integrated circuit
Abstract:
A method for placing a system on a structured application specific integrated circuit (ASIC) using an electronic design automation tool is disclosed. A subregion that includes an illegal position in a placement solution is identified. All structured ASIC cells in the subregion are removed. Positions for all the structured ASIC cells that are legal are determined.
Abstract(Chinese):

公开了一种使用电子设计自动化工具将系统放置在结构化专用集成电路（ASIC）上的方法。 确定在放置解决方案中包含非法位置的分区域。 该子区域中的所有结构化ASIC单元被去除。 确定合法的所有结构化ASIC单元的位置。

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