Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells (16) not to be wire bonded, on which ESD (electrostatic discharge) protection circuits (4) having ESD protection transistors are amounted, are disposed between the respective I/O cells (14), whereby the chip size is reduced upon consideration of layout of the electrode pads.