Invention Grant
- Patent Title: Semiconductor device including interconnects, vias connecting the interconnects and greater thickness of the liner film adjacent the vias
- Patent Title (中): 包括互连的半导体器件，连接互连的通孔和邻近过孔的衬垫膜的较大厚度
-
Application No.: US12437944Application Date: 2009-05-08
-
Publication No.: US08035232B2Publication Date: 2011-10-11
- Inventor: Takeshi Harada , Junichi Shibata , Akira Ueki
- Applicant: Takeshi Harada , Junichi Shibata , Akira Ueki
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-125135 20080512
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating film. A liner insulating film is formed on the upper surfaces of the interlayer insulating film and lower-level interconnects. An interlayer insulating film is formed on the upper surface of the liner insulating film. Upper-level interconnects are formed in the interlayer insulating film. The lower-level interconnects and the upper-level interconnects are connected with each other through vias. Parts of the liner insulating film formed in via-adjacent regions have a greater thickness than a part thereof formed outside the via-adjacent regions.
Public/Granted literature
- US20090278261A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2009-11-12
Information query
IPC分类:
