Disclosed is a charge-controlling semiconductor integrated circuit including: a current-controlling MOS transistor; a current detection circuit including a 1/N size current-detecting MOS transistor; and a gate voltage control circuit, wherein the current detection circuit includes an operational amplifier circuit, a bias condition of the current-detecting MOS transistor becomes same as the current-controlling MOS transistor based on an operational amplifier circuit output, voltage drops in lines from drain electrode to a corresponding input point of the operational amplifier circuit become the same by a parasitic resistance, and when the output of the operational amplifier circuit is applied to a control terminal of the bias condition controlling transistor, the drain voltages become the same potential, and the line from the drain electrode of the current-detecting MOS transistor to the input point is formed to be redundantly arranged inside the chip so that a parasitic resistance becomes a predetermined value.