Invention Grant
US08036300B2 Dual loop clock recovery circuit 有权
双回路时钟恢复电路

Dual loop clock recovery circuit
Abstract:
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.
Public/Granted literature
Information query
Patent Agency Ranking
0/0