Invention Grant
- Patent Title: Dual loop clock recovery circuit
- Patent Title (中): 双回路时钟恢复电路
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Application No.: US12456078Application Date: 2009-06-11
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Publication No.: US08036300B2Publication Date: 2011-10-11
- Inventor: William P. Evans , Eric Naviasky
- Applicant: William P. Evans , Eric Naviasky
- Applicant Address: US CA Los Altos
- Assignee: Rambus, Inc.
- Current Assignee: Rambus, Inc.
- Current Assignee Address: US CA Los Altos
- Agency: Holland & Knight LLP
- Agent Brian J. Colandreo, Esq.; Mark H. Whittenberger, Esq
- Main IPC: H04B7/02
- IPC: H04B7/02 ; H04L7/00 ; G06J1/00

Abstract:
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.
Public/Granted literature
- US20090257542A1 Dual loop clock recovery circuit Public/Granted day:2009-10-15
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