Invention Grant
US08037252B2 Method for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor
有权
用于通过选择性目录更新来减少基于目录的相干多处理器中未修改的高速缓存块的一致性执行的方法
- Patent Title: Method for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor
- Patent Title (中): 用于通过选择性目录更新来减少基于目录的相干多处理器中未修改的高速缓存块的一致性执行的方法
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Application No.: US11845812Application Date: 2007-08-28
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Publication No.: US08037252B2Publication Date: 2011-10-11
- Inventor: Farnaz Toussi
- Applicant: Farnaz Toussi
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.
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