Invention Grant
US08037378B2 Automatic test entry termination in a memory device 有权
存储设备中的自动测试条目终止

Automatic test entry termination in a memory device
Abstract:
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test mode is disabled. If the appropriate key is received, the test mode is continued to be enabled until it is expressly disabled by the user.
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