Invention Grant
- Patent Title: Solder bump with inner core pillar in semiconductor package
- Patent Title (中): 半导体封装中内芯柱焊接凸块
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Application No.: US11859416Application Date: 2007-09-21
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Publication No.: US08039960B2Publication Date: 2011-10-18
- Inventor: Yaojian Lin
- Applicant: Yaojian Lin
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Robert D. Atkins Patent Law Group
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An electrical interconnect within a semiconductor device consists of a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, first barrier layer, adhesion layer, and seed layer are formed over the substrate. An inner core pillar including a hollow interior is centered over and formed within a footprint of the contact pad. A second barrier layer and a wetting layer are formed over the single cylindrical inner core pillar and hollow interior. A spherical bump is formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad. The spherical bump is electrically connected to the contact pad.
Public/Granted literature
- US20090079094A1 Solder Bump with Inner Core Pillar in Semiconductor Package Public/Granted day:2009-03-26
Information query
IPC分类: