Invention Grant
- Patent Title: Semiconductor integrated circuit
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Application No.: US12890253Application Date: 2010-09-24
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Publication No.: US08040170B2Publication Date: 2011-10-18
- Inventor: Masaya Sumita
- Applicant: Masaya Sumita
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2002-161979 20020603
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.
Public/Granted literature
- US20110012656A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2011-01-20
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