Invention Grant
- Patent Title: Phase-locked loop
- Patent Title (中): 锁相环
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Application No.: US12113346Application Date: 2008-05-01
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Publication No.: US08040190B2Publication Date: 2011-10-18
- Inventor: David Ruffieux
- Applicant: David Ruffieux
- Applicant Address: CH Neuchatel
- Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique SA-Recherche et Developpement
- Current Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique SA-Recherche et Developpement
- Current Assignee Address: CH Neuchatel
- Agency: Young & Thompson
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
A phase-locked loop includes: a variable oscillator connected to a first resonator, said oscillator being able to deliver an output signal at a first output frequency Fout1, a first frequency divider receiving the output signal and able to convert it into a divided frequency signal Fout1/n, a reference oscillator connected to a second so-called reference resonator, delivering a reference signal at a low reference frequency Fref, generating an electrical dissipation lower than a microampere, a phase comparator measuring the phase error between the divided frequency signal Fout1/n and the reference signal and being able to produce a test signal, a low-pass filter or an integrating circuit able to filter the test signal and able to generate a voltage or a control word designed to control the voltage-controlled or digitally controlled oscillator.
Public/Granted literature
- US20090273402A1 PHASE-LOCKED LOOP Public/Granted day:2009-11-05
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