Invention Grant
- Patent Title: Interpolative all-digital phase locked loop
- Patent Title (中): 内插全数字锁相环
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Application No.: US12022931Application Date: 2008-01-30
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Publication No.: US08045670B2Publication Date: 2011-10-25
- Inventor: Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
- Applicant: Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
Public/Granted literature
- US20080317187A1 Interpolative All-Digital Phase Locked Loop Public/Granted day:2008-12-25
Information query
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