Invention Grant
- Patent Title: Electronic component placement method
- Patent Title (中): 电子元件放置方法
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Application No.: US11916473Application Date: 2006-08-16
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Publication No.: US08046907B2Publication Date: 2011-11-01
- Inventor: Hideki Sumi , Takahiro Noda
- Applicant: Hideki Sumi , Takahiro Noda
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JP2005-238166 20050819
- International Application: PCT/JP2006/316438 WO 20060816
- International Announcement: WO2007/021026 WO 20070222
- Main IPC: B23P19/00
- IPC: B23P19/00

Abstract:
In an electronic component placement method in which electronic components are picked up from a plurality of component supply sections which supply electronic components using a plurality of mounting heads which are provided corresponding to the respective component supply sections, and the electronic components are transferred and mounted on a substrate in a same placing stage, in performing the component transferring and mounting operations, head interference areas which constitute exclusive operating regions to which only the specified mounting heads are allowed to access are set for every placing turn. Due to such a constitution, in the component placement operation, it is possible to rationally set the accessible region without causing the interference of one mounting head with another mounting head thus shortening a placing tact time by excluding wasteful standby times of the mounting heads.
Public/Granted literature
- US20090100672A1 ELECTRONIC COMPONENT PLACEMENT METHOD Public/Granted day:2009-04-23
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