Invention Grant
- Patent Title: Semiconductor integrated circuit device fabrication method
- Patent Title (中): 半导体集成电路器件制造方法
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Application No.: US11463467Application Date: 2006-08-09
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Publication No.: US08048614B2Publication Date: 2011-11-01
- Inventor: Yoshihiko Okamoto , Masami Ogita
- Applicant: Yoshihiko Okamoto , Masami Ogita
- Applicant Address: JP Kikugawa-shi
- Assignee: Yoshihiko Okamoto
- Current Assignee: Yoshihiko Okamoto
- Current Assignee Address: JP Kikugawa-shi
- Agency: Apex Juris, pllc
- Agent Tracy M. Heims
- Priority: JPJP2004-031528 20040205
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.
Public/Granted literature
- US20070117409A1 Aligner and Semiconductor Device Manufacturing Method Using the Aligner Public/Granted day:2007-05-24
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