Invention Grant
US08048704B2 Method of forming a MEMS topped integrated circuit with a stress relief layer
有权
用应力消除层形成MEMS顶部集成电路的方法
- Patent Title: Method of forming a MEMS topped integrated circuit with a stress relief layer
- Patent Title (中): 用应力消除层形成MEMS顶部集成电路的方法
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Application No.: US12750145Application Date: 2010-03-30
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Publication No.: US08048704B2Publication Date: 2011-11-01
- Inventor: Peter Smeys , Peter Johnson
- Applicant: Peter Smeys , Peter Johnson
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Mark C. Pickering
- Main IPC: H01L33/12
- IPC: H01L33/12 ; H01L29/82 ; H01L21/268
Abstract:
The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.
Public/Granted literature
- US20100190311A1 Method of Forming a MEMS Topped Integrated Circuit with a Stress Relief Layer Public/Granted day:2010-07-29
Information query
IPC分类:
