Invention Grant
- Patent Title: Method for filling multi-layer chip-stacked gaps
- Patent Title (中): 填充多层芯片堆叠间隙的方法
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Application No.: US12727033Application Date: 2010-03-18
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Publication No.: US08048721B2Publication Date: 2011-11-01
- Inventor: Hung-Hsin Hsu , Wei-Chih Chien
- Applicant: Hung-Hsin Hsu , Wei-Chih Chien
- Applicant Address: TW Hsinchu
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity.
Public/Granted literature
- US20110230012A1 METHOD FOR FILLING MULTI-LAYER CHIP-STACKED GAPS Public/Granted day:2011-09-22
Information query
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