Invention Grant
- Patent Title: Semiconductor device with large blocking voltage
- Patent Title (中): 半导体器件具有较大的阻断电压
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Application No.: US12126887Application Date: 2008-05-25
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Publication No.: US08049223B2Publication Date: 2011-11-01
- Inventor: Haruka Shimizu , Hidekatsu Onose
- Applicant: Haruka Shimizu , Hidekatsu Onose
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2007-183917 20070713
- Main IPC: H01L29/04
- IPC: H01L29/04 ; H01L29/24

Abstract:
A junction FET having a large gate noise margin is provided. The junction FET comprises an n− layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n− layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.
Public/Granted literature
- US20090014719A1 SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE Public/Granted day:2009-01-15
Information query
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