Invention Grant
- Patent Title: Semiconductor apparatus, manufacturing method for the semiconductor apparatus, and electronic information device
- Patent Title (中): 半导体装置，半导体装置的制造方法以及电子信息装置
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Application No.: US12320446Application Date: 2009-01-27
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Publication No.: US08049344B2Publication Date: 2011-11-01
- Inventor: Yasunori Kitamura
- Applicant: Yasunori Kitamura
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Edwards Angell Palmer & Dodge LLP
- Priority: JP2008-046854 20080227
- Main IPC: H01L23/544
- IPC: H01L23/544
Abstract:
A semiconductor apparatus according to the present invention includes one or a plurality of pairs of a standard pattern and an offset pattern formed therein with respect to the standard pattern as manufacturing information and other information at an information writing position, which is visible from the outside, of each semiconductor chip on a wafer.
Public/Granted literature
Information query
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