Invention Grant
- Patent Title: ΔΣ modulation circuit and system
- Patent Title (中): &Dgr;&Sgr 调制电路和系统
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Application No.: US12686973Application Date: 2010-01-13
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Publication No.: US08049651B2Publication Date: 2011-11-01
- Inventor: Hiroyuki Nakamoto
- Applicant: Hiroyuki Nakamoto
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2009-042280 20090225
- Main IPC: H03M3/00
- IPC: H03M3/00

Abstract:
A ΔΣ modulation circuit that includes a first integrator and second integrator coupled in series, a quantizer coupled to an output of the second integrator, a delay device disposed in a feedback path from an output of the quantizer to an input of the first and second integrators, an adder which generates a difference between an output and an input of the quantizer, and a feedback circuit including a delay device which couples an output of the adder to an output of one of the first and second integrators.
Public/Granted literature
- US20100214143A1 deltasigma MODULATION CIRCUIT AND SYSTEM Public/Granted day:2010-08-26
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