Invention Grant
- Patent Title: NAND flash memory with integrated bit line capacitance
- Patent Title (中): 具有集成位线电容的NAND闪存
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Application No.: US12474463Application Date: 2009-05-29
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Publication No.: US08050092B2Publication Date: 2011-11-01
- Inventor: Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
- Applicant: Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
- Applicant Address: US CA Scotts Valley
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Scotts Valley
- Agency: Fellers, Snider, et al.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C11/24

Abstract:
Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
Public/Granted literature
- US20100302849A1 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE Public/Granted day:2010-12-02
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