Invention Grant
US08050104B2 Non-volatile memory device and system having reduced bit line bias time
失效
具有降低的位线偏置时间的非易失性存储器件和系统
- Patent Title: Non-volatile memory device and system having reduced bit line bias time
- Patent Title (中): 具有降低的位线偏置时间的非易失性存储器件和系统
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Application No.: US12697550Application Date: 2010-02-01
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Publication No.: US08050104B2Publication Date: 2011-11-01
- Inventor: Dae Seok Byeon
- Applicant: Dae Seok Byeon
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2009-0009884 20090206
- Main IPC: G11C11/4193
- IPC: G11C11/4193

Abstract:
A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.
Public/Granted literature
- US20100202216A1 NON-VOLATILE MEMORY DEVICE AND SYSTEM HAVING REDUCED BIT LINE BIAS TIME Public/Granted day:2010-08-12
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