Invention Grant
- Patent Title: Digital phase locked loop with integer channel mitigation
- Patent Title (中): 数字锁相环,整数通道缓解
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Application No.: US12024881Application Date: 2008-02-01
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Publication No.: US08050375B2Publication Date: 2011-11-01
- Inventor: Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
- Applicant: Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
Public/Granted literature
- US20080317188A1 Digital Phase Locked Loop with Integer Channel Mitigation Public/Granted day:2008-12-25
Information query
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