A general-purpose register file including a plurality of general-purpose registers stores parallel arithmetic data. A plurality of pattern registers store a plurality of items of pattern data indicating the rearrangement of data in bytes, in half words, in words, or in a combination of these units. A data select circuit selects one of the items of pattern data stored in the plurality of pattern registers according to specifying data included in an instruction. A rearranging circuit rearranges parallel arithmetic data according to the item of pattern data selected by the data select circuit.