Invention Grant
US08051238B2 On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture
有权
具有互连开关点的片上总线架构，使用其的半导体器件以及用于在片上总线架构中传送数据的方法
- Patent Title: On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture
- Patent Title (中): 具有互连开关点的片上总线架构，使用其的半导体器件以及用于在片上总线架构中传送数据的方法
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Application No.: US11244482Application Date: 2005-10-06
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Publication No.: US08051238B2Publication Date: 2011-11-01
- Inventor: Chae-Eun Rhee
- Applicant: Chae-Eun Rhee
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec
- Priority: KR10-2004-0080009 20041007
- Main IPC: G06F13/00
- IPC: G06F13/00 ; H04L12/28
Abstract:
An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.
Public/Granted literature
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