Invention Grant
- Patent Title: Performance-aware logic operations for generating masks
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Application No.: US12212088Application Date: 2008-09-17
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Publication No.: US08051392B2Publication Date: 2011-11-01
- Inventor: Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
- Applicant: Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F7/66 ; G06K9/00 ; H01L21/66

Abstract:
A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.
Public/Granted literature
- US08122394B2 Performance-aware logic operations for generating masks Public/Granted day:2012-02-21
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