Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.