Invention Grant
US08053369B2 Process for forming opening portion in interlayer insulation film on metallic layer of semiconductor device
失效
在半导体器件的金属层上形成层间绝缘膜的开口部分的工艺
- Patent Title: Process for forming opening portion in interlayer insulation film on metallic layer of semiconductor device
- Patent Title (中): 在半导体器件的金属层上形成层间绝缘膜的开口部分的工艺
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Application No.: US12613276Application Date: 2009-11-05
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Publication No.: US08053369B2Publication Date: 2011-11-08
- Inventor: Akihiro Takase
- Applicant: Akihiro Takase
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2008-285373 20081106
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L23/48
Abstract:
A manufacturing method for a semiconductor device, including: forming a metallic layer and an interlayer insulation film on a semiconductor substrate sequentially; etching on the interlayer insulation film using fluorine-based etching gas to form an opening portion of a predetermined pattern, reaching the metallic layer; and supplying chlorine-based silane gas and discharging, thus forming a Si film at least on an internal surface of the opening portion without exposure to the atmosphere after the etching.
Public/Granted literature
- US20100112813A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE Public/Granted day:2010-05-06
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