Invention Grant
- Patent Title: Semiconductor device and layout method thereof
- Patent Title (中): 半导体器件及其布局方法
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Application No.: US12320785Application Date: 2009-02-04
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Publication No.: US08053813B2Publication Date: 2011-11-08
- Inventor: Kazuyuki Morishige
- Applicant: Kazuyuki Morishige
- Applicant Address: JP Chuo-ku, Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Chuo-ku, Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-028211 20080207
- Main IPC: H01L27/118
- IPC: H01L27/118

Abstract:
A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion.
Public/Granted literature
- US20090200579A1 Semiconductor device and layout method thereof Public/Granted day:2009-08-13
Information query
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