Invention Grant
- Patent Title: Isolated stacked die semiconductor packages
- Patent Title (中): 隔离堆叠裸片半导体封装
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Application No.: US12949587Application Date: 2010-11-18
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Publication No.: US08053883B2Publication Date: 2011-11-08
- Inventor: Manolito Galera , Leocadio Morona Alabin
- Applicant: Manolito Galera , Leocadio Morona Alabin
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kirton & McConkie
- Agent Kenneth E. Horton
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.
Public/Granted literature
- US20110062570A1 ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES Public/Granted day:2011-03-17
Information query
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