Invention Grant
- Patent Title: Fully integrated on-chip low dropout voltage regulator
- Patent Title (中): 全集成片上低压差稳压器
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Application No.: US12347425Application Date: 2008-12-31
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Publication No.: US08054055B2Publication Date: 2011-11-08
- Inventor: Sajal Kumar Mandal
- Applicant: Sajal Kumar Mandal
- Applicant Address: IN Greater Noida
- Assignee: STMicroelectronics PVT. Ltd.
- Current Assignee: STMicroelectronics PVT. Ltd.
- Current Assignee Address: IN Greater Noida
- Agency: Hogan Lovells US LLP
- Agent William J. Kubida; Peter J. Meza
- Priority: IN3532/DEL/2005 20051230
- Main IPC: G05F1/56
- IPC: G05F1/56

Abstract:
A low dropout voltage regulator (LDO) includes a bias voltage generator, a differential error amplifier, an output driver, a controlled active load, a Double Ended Cascode Miller compensation block. The bias voltage generator produces a plurality of bias voltages. The differential error amplifier produces a differential output voltage based on the difference between a reference voltage and a function of the output voltage. The input terminal of the output driver is coupled to one output of the differential error amplifier. The substrate terminal of the output driver is capacitively coupled to the output node and resistively coupled to the input supply node. The controlled active load is coupled to the output of the output driver, and its control terminal is coupled to a function of the second output of the differential error amplifier. The inputs of the Double Ended Cascode Miller compensation block are capacitively coupled to the output node and its output is coupled to the input terminal of the output driver.
Public/Granted literature
- US20090128104A1 FULLY INTEGRATED ON-CHIP LOW DROPOUT VOLTAGE REGULATOR Public/Granted day:2009-05-21
Information query
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