Invention Grant
US08055697B2 Method and device for dynamically verifying a processor architecture
有权
用于动态验证处理器架构的方法和设备
- Patent Title: Method and device for dynamically verifying a processor architecture
- Patent Title (中): 用于动态验证处理器架构的方法和设备
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Application No.: US12057623Application Date: 2008-03-28
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Publication No.: US08055697B2Publication Date: 2011-11-08
- Inventor: Priyadarsan Patra
- Applicant: Priyadarsan Patra
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schawbe, Williamson & Wyatt, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A method and device may be useful for dynamically verifying a processor architecture at runtime. The checker may more efficiently and cheaply verify at least some of the functionality provided by the execution unit of the processor architecture. The checker may verify operations such as addition, subtraction, multiplication, and division.
Public/Granted literature
- US20090248781A1 METHOD AND DEVICE FOR DYNAMICALLY VERIFYING A PROCESSOR ARCHITECTURE Public/Granted day:2009-10-01
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