Invention Grant
US08055885B2 Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse 有权
用于实现指令重用的数据处理装置,以及用于存储用于实现指令重用的数据处理程序的数字数据存储介质

  • Patent Title: Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse
  • Patent Title (中): 用于实现指令重用的数据处理装置,以及用于存储用于实现指令重用的数据处理程序的数字数据存储介质
  • Application No.: US10593695
    Application Date: 2005-03-25
  • Publication No.: US08055885B2
    Publication Date: 2011-11-08
  • Inventor: Yasuhiko Nakashima
  • Applicant: Yasuhiko Nakashima
  • Applicant Address: JP Saitama
  • Assignee: Japan Science and Technology Agency
  • Current Assignee: Japan Science and Technology Agency
  • Current Assignee Address: JP Saitama
  • Agency: Nixon & Vanderhye P.C.
  • Priority: JP2004-097197 20040329; JP2004-266056 20040913; JP2004-324348 20041108; JP2004-347124 20041130
  • International Application: PCT/JP2005/005591 WO 20050325
  • International Announcement: WO2005/093562 WO 20051006
  • Main IPC: G06F9/00
  • IPC: G06F9/00
Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse
Abstract:
A method and apparatus is provided for significantly speeding-up program execution in a data processing device. The data processing device is provided with a specialized instruction region storage section comprising content addressable memory (CAM) and random access memory (RAM) that operatively functions as an instruction sequence reuse table which is capable of registering/storing sequences of program instructions and corresponding instruction sequence output data as input/output (I/O) groups for potential future use in place of re-executing identical portions of program code. The data processing device includes at least one instruction stream processor which includes a computing unit for executing instructions and a dependency relationship analysis unit or “reuse window” unit (RW) that analyzes instruction sequence patterns from regions of instructions stored in a main memory to determine if the patterns can be divided up into smaller partitions that have no interdependencies and hence are potential candidates for reuse.
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