Invention Grant
US08056069B2 Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
失效
用于SIMD向量化的连续存储器访问的集成的内部和组间集成的框架
- Patent Title: Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
- Patent Title (中): 用于SIMD向量化的连续存储器访问的集成的内部和组间集成的框架
-
Application No.: US11856284Application Date: 2007-09-17
-
Publication No.: US08056069B2Publication Date: 2011-11-08
- Inventor: Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu
- Applicant: Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: VanLeeuwen & VanLeeuwen
- Agent Matthew B. Talpis
- Main IPC: G06F9/45
- IPC: G06F9/45 ; G06F7/52 ; G06F15/00

Abstract:
A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.
Public/Granted literature
Information query