Invention Grant
US08058655B2 Vertical junction field effect transistors having sloped sidewalls and methods of making
有权
具有倾斜侧壁的垂直结型场效应晶体管和制造方法
- Patent Title: Vertical junction field effect transistors having sloped sidewalls and methods of making
- Patent Title (中): 具有倾斜侧壁的垂直结型场效应晶体管和制造方法
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Application No.: US12613065Application Date: 2009-11-05
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Publication No.: US08058655B2Publication Date: 2011-11-15
- Inventor: David C. Sheridan , Andrew P. Ritenour
- Applicant: David C. Sheridan , Andrew P. Ritenour
- Applicant Address: US MS Jackson
- Assignee: SS SC IP, LLC
- Current Assignee: SS SC IP, LLC
- Current Assignee Address: US MS Jackson
- Agency: Morris, Manning & Martin, LLP
- Agent Christopher W. Raimund
- Main IPC: H01L29/24
- IPC: H01L29/24 ; H01L49/00
Abstract:
Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of
Public/Granted literature
- US20100148186A1 VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING Public/Granted day:2010-06-17
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